Recent semiconductor devices have not only been scaled up and speeded up, but also been systematized by incorporating many functions. In order to scale up and speed up semiconductor devices, transistors have been made finer, and operating speeds have been improved while power source voltages have been reduced. Various types of function blocks including a CPU and various types of memory devices are combined with each other for systematization. Those memory devices jointly mounted on system LSIs are similarly required to operate at a high speed and a low power source voltage. For example, a Static Random Access Memory (SRAM), hereinafter abbreviated as SRAM, which is jointly mounted for applications of a cache memory and the like, is similarly required to operate at a high speed and a low power source voltage.
A conventional SRAM will be described with reference to FIG. 1. FIG. 1 shows a conventional SRAM memory cell (hereinafter referred to as an SRAM cell) formed by six transistors. When a word line WL has a low potential, data can be held stably by forming a loop with two CMOS (Complementary Metal Oxide Semiconductor) inverters. Specifically, one of the CMOS inverters uses a storage node V1 as an input and outputs inverse data of data stored in the storage node V1 to a storage node V2. The other of the CMOS inverters uses the storage node V2 as an input and outputs inverse data of data stored in the storage node V2 to the storage node V1.
When the word line WL is accessed and brought into a high potential, access transistors N3 and N4 are brought into conduction so as to read data stored in the storage nodes V1 and V2 into bit lines BLT and BLN, thereby performing a reading operation of the memory. Conversely, data from the bit lines BLT and BLN are written into the storage nodes V1 and V2, thereby performing a writing operation of the memory.
However, there has been a problem that a rate of increase in delay time when a power source voltage Vdd is lowered in a conventional SRAM cell is larger than a rate of increase in delay time of a CMOS inverter circuit. Furthermore, a problem of corruption of stored data also arises when a reading operation is performed at a low power source voltage. FIG. 2 shows the dependence of delay time (normalized delay time T) of an SRAM cell and a CMOS inverter circuit on power source voltages (Vdd). In FIG. 2, a line A represents a delay time of an SRAM cell, and a line B represents a delay time of a CMOS inverter circuit. A rate of increase in delay time of the SRAM cell becomes higher when a power source voltage is lowered. Furthermore, if a reading operation is performed at not more than a certain power source voltage (indicated by “a”), then stored data are corrupted, so that the SRAM cell does not work.
The corruption of stored data in the reading operation will be described with reference to FIGS. 3A to 3C. FIG. 3A shows a waveform of the word line WL, FIG. 3B shows a waveform of the storage nodes in a normal reading operation, and FIG. 3C shows a waveform of the storage nodes when data are corrupted in a reading operation. Here, it is assumed that the storage node V1 has a low potential “0” while the storage node V2 has a high potential “1.” As shown in FIG. 3A, when the word line WL is accessed and brought into a high potential, the storage nodes V1 and V2 are brought into conduction with a pair of bit lines BLT and BLN via the access transistors N3 and N4. Thus, the low potential of the storage node V1 is increased by the bit line BLT that has been pre-charged into a high potential.
As shown in FIG. 3B, in a case of storage nodes in a normal cell, a normal reading operation is performed while a low potential “0” of a storage node is slightly increased from the ground potential. However, as shown in FIG. 3C, if the inverter circuit (transistors P2 and N2) has a varied threshold voltage, which is low, then the potential of the storage node V1 reaches the threshold voltage of the inverter circuit (transistors P2 and N2), thereby lowering a high potential “1” of the storage node V2. The reduction in the storage node V2 causes further increase of the potential of the storage node V1. As a result, corruption D of stored data is caused in a reading operation, and the stored data are overwritten with inverse data.
Generally, a Static Noise Margin (SNM) is used as an index for measuring the stability of holding accessed data in an SRAM cell. As shown in FIG. 4, an SRAM cell is separated into two inverters, and DC (direct current) characteristics are calculated for each inverter. When those two DC characteristics are superimposed so that a DC characteristic output of one of the inverters serves as a DC characteristic input of the other inverter, a butterfly curve is drawn. An SNM is defined as one side of a maximum square inscribed in this butterfly curve. When an SNM is 0 mV or more, a normal reading operation is performed as shown in FIG. 3B. When an SNM is 0 mV or less, stored data are overwritten with inverse data in a reading operation as shown in FIG. 3C.
Predictions for the future of the SNM have been made in Reference 1 (A. J. Bhavnagarwala, “The impact of intrinsic device fluctuations on CMOS SRAM cell stability,” IEEE Journal of Solid State Circuit, Vol. 36, No. 4, April 2001 (FIGS. 5, 10A, and 10B)). Specifically, when channel lengths of transistors used are made shorter so that they are shifted from 250 nm to 50 nm as shown in FIG. 5, an average of the SNMs is not only decreased, but a deviation of the SNMs is increased. Accordingly, the worst value of the SNMs is considerably lowered. The worst value of the SNMs becomes below “0” in the illustrated example of 50 nm. Accordingly, stored data are corrupted when the word line WL is brought into a high potential in a reading operation.
Meanwhile, an SRAM having a read-only port has been proposed in Reference 2 (H. Sakakibara, “A 750 MHz 144 Mb cache DRAM LSI with speed scalable design and programmable at-speed function-array BIST,” IEEE International Solid State Circuit Conference, 2003 (FIG. 1)). In this SRAM, as shown in FIG. 6, a memory cell is formed by eight transistors, and a full swing is taken on a read-only bit line with a cell current of the memory cell. The original purpose of this system is to obtain an improved effect of operating speeds in further developed generations. Furthermore, corruption of stored data in a reading operation, which would become problematic in a conventional SRAM, is not caused because no electric charges flow from the bit line into storage nodes in the cell during the reading operation. Accordingly, an SRAM having this circuit structure can operate not only at a high speed but also with stability even in further developed generations.
In the conventional SRAM cell using six transistors as in Reference 1, the worst value of SNMs is lowered. Accordingly, there is a problem that data will become difficult to be stably held in future. On the other hand, in the SRAM cell having a read-only port as in Reference 2, no corruption of stored data is caused in a reading operation. However, there is a problem that a cell area is increased because the number of transistors is eight and five control signals are required.